The present invention relates to a method of programming a row of antifuse memory cells by breaking down at least N antifuse elements in the memory cells, with the breakdown comprising application of a breakdown voltage to an anode of each antifuse element.
The use of antifuse memory cells in integrated circuits allows a low cost realization of non-volatile memory areas having an average but sufficient storing capacity for recording a small amount of permanent data, such as an integrated circuit serial number, a secret code, parameter data of the integrated circuit""s analog variables, etc. In a general way, memories of the fuse or antifuse type are an advantageous alternative to non-volatile memories based on the principle of electrical charge retention, using for example, floating gate transistors.
A memory cell of the fuse type comprises a fuse element, for example, a fuse made of polysilicon. This is initially conductive and becomes non-conductive when it is broken down. The breakdown is caused by a laser or is obtained by application of a breakdown voltage. On the contrary, an antifuse memory cell comprises an antifuse element, generally an oxide layer, which is initially insulated and becomes conductive after breakdown. The breakdown causes a conductive path to appear in the oxide.
Between these two technologies (fuse or antifuse), the antifuse is at present the best approach in terms of integration density and flexibility. However, antifuse memories have a rather long programming time, which is a major drawback in some applications, such as in a large scale production of integrated circuits each comprising an antifuse memory area to be programmed, for example. To aid in better understanding, the collective breakdown of 20 antifuse elements requires the application of a breakdown voltage during a time of about 50 ms. This time is not negligible in the field of microelectronics, where programming times generally are on the order of some tens of milliseconds or some milliseconds rather than several tens of milliseconds.
As a reminder, FIG. 1 illustrates the conventional arrangement of N antifuse elements AF1, AF2 . . . AFN during their breakdown. The antifuse elements are shown like capacitors and the insulating material between the electrodes of the capacitors forms the antifuse element. The cathodes of the antifuse elements are coupled to ground and the anodes are coupled to a common node N1. Node N1 is coupled to a source of voltage Vhv by a switch SWg. The switch SWg is closed during a predetermined time t(N), during which the antifuse elements receive the breakdown voltage Vhv on their anodes. The breakdown of the antifuse material causes a serial resistance Rc between the electrodes which renders the antifuse element conductive.
These antifuse elements are arranged in a row of memory cells comprising selection, access and read circuitry which are not shown here for the sake of simplicity. The programming of the row of memory cells corresponds to the breakdown of the antifuse elements. FIG. 2 is a graph showing the breakdown time t(N) versus the number N of antifuse elements which are collectively broken down. It appears that time t(N) is not constant and depends on the number N. More particularly, this graph is not linear and tends to increase in a pseudo-exponential way with number N.
In view of the foregoing background, an object of the present invention is to reduce the breakdown time of a group of N antifuse elements.
In particular, the present invention aims at solving the problem by rapidly increasing the breakdown time in relation to the number N of antifuse elements to be broken down. In a general way, the present invention provides a method of programming antifuse memory cells for decreasing the breakdown time of a group of N antifuse elements.
To achieve this object, the present invention provides a method of programming a row of parallel antifuse memory cells comprising a step of breaking down at least N antifuse elements in the memory cells, with the breakdown of an antifuse element comprising the application of a breakdown voltage to the anode of each antifuse element. The antifuse elements are sequentially broken down by groups of P antifuse elements, with P being less than N and at least equal to 1. The antifuse elements of a same group simultaneously receive the breakdown voltage. The breakdown of a next group of antifuse elements immediately takes place after the breakdown of a previous group of antifuse elements.
According to one embodiment, P is equal to 1, and the antifuse elements are individually broken down one after the other. According to another embodiment, P is chosen among several possible values so that the total breakdown time of the N antifuse elements is optimal. According to yet another embodiment, the number P of simultaneously broken down antifuse elements is not constant during the programming of the row of memory cells.
The method preferably further comprises detecting the breakdown of the antifuse elements. According to one embodiment, P next antifuse elements are not broken down as long as the breakdown of P previous antifuse elements has not been detected. The breakdown of an antifuse element may be detected when a voltage greater than a predetermined threshold appears on the cathode of the antifuse element while its anode receives the breakdown voltage.
The method may be applied to a memory comprising rows of cells arranged in word lines and bit lines, and the programming of a row of cells comprises the selection of a word line and the sequential application of the breakdown voltage to the bit lines, by groups of P bit lines receiving the breakdown voltage simultaneously.
The method may also be applied to a row of antifuse memory cells having a differential architecture, with each memory cell comprising two antifuse elements. The programming of each cell comprises the breakdown of an antifuse element chosen among the two antifuse elements of the cell according to the value of a binary data to be programmed. The breakdown of the row of cells comprises the sequential breakdown of only one antifuse element in each cell of the row.
The present invention also relates to an antifuse integrated circuit memory comprising at least one row of parallel antifuse memory cells. The memory cells are programmable by breaking down N antifuse elements in the memory cells. The memory preferably comprises means for programming the row of cells by application of a breakdown voltage to an anode of each antifuse element to be broken down. The means for programming comprise means for sequentially applying the breakdown voltage to groups of P antifuse elements, with P being less than N and at least equal to 1. The antifuse elements of a same group simultaneously receive the breakdown voltage. The breakdown of a next group of antifuse elements immediately takes place after the breakdown of a previous group of antifuse elements.
According to one embodiment, P is equal to 1 and the means for programming apply the breakdown voltage individually to the antifuse elements so that the antifuse elements are broken down one after the other. According to another embodiment, the number P of antifuse elements in the groups of simultaneously broken down antifuse elements is not constant during the programming of a row of memory cells.
The memory further comprises means for detecting the breakdown of antifuse elements, and delivering a breakdown detection signal. The means for programming are arranged so that the breakdown voltage is not to be applied to a next group of antifuse elements as long as the breakdown of a previous group has not been detected.
The detection means may comprise at least one comparator having a first input coupled to the cathode of at least one antifuse element, a second input receiving a reference voltage and an output delivering the breakdown detection signal.
The memory may also comprise a sequential circuit and switches driven by the sequential circuit for sequentially applying the breakdown voltage to the antifuse elements. The sequential circuit receives the breakdown detection signal.
The memory may comprise several rows of cells arranged in word lines and bit lines, with each bit line comprising a distribution line for the breakdown voltage. The means for programming are arranged to select a word line and apply the breakdown voltage sequentially to the distribution lines of the bit lines, by groups of P bit lines receiving the breakdown voltage simultaneously.
The memory may also comprise memory cells having a differential architecture, and each comprises two parallel antifuse elements, and switches for selecting an antifuse element to be broken down among the two according to the value of a binary data to be recorded.